An FPGA ('Field Programmable Gate Array') is an integrated circuit comprising a large number of programmable and interconnectable logic resources, enabling the programmable implementation of a digital electronic circuit such as a microprocessor, a computational gas pedal or a complex hybrid system-on-a-chip. FPGAs are widely used in integrated circuit design, as they enable prototype circuits to be produced very quickly, without having to manufacture the chip on silicon. However, some circuits are too large to be implemented on a single FPGA. To solve this problem, it is possible to use a platform made up of several highly interconnected FPGAs, which can be considered as a single virtual FPGA giving access to all the platform's resources. This solution, while elegant, poses several problems. In particular, existing tools do not take into account all the constraints of the placement problem to be solved in order to efficiently map a circuit on a multi-FPGA platform. For example, current cost functions are not designed to minimize signal propagation times between FPGA registers, nor to take into account capacity constraints induced by connection routing. The aim of this PhD work is to design hypergraph partitioning and placement models adapted to the problem of circuit placement on a multi-FPGA platform. These models will be specifically designed to meet the objectives and performance criteria defined by circuit designers.